Semiconductor memories have been known each of which contains alternative redundant memory cells provided in the row direction, in addition to memory cells normally used in system operations. In such a semiconductor memory, a redundant memory cell has a larger area than a normal memory cell. An alternative redundant memory cell and a defective normal memory cell are selected double. In the configuration, since a redundant memory cell has a larger area than a normal memory cell, correct data of the redundant memory cell is output even when the normal memory cell and the redundant memory cell are selected double.
Semiconductor memories with a redundant circuit have also been known which connect a high-sensitivity sense amplifier containing a transistor having a high drivability which is higher than the drivability of a sense amplifier used for a normal memory cell array to a spare cell in a spare row.
When the redundant memory cells are provided in the row direction as described above, the area of the corresponding sense amplifier may be increased with the increase in area of the redundant memory cells. As a result, the areas of the sense amplifiers increase in all columns. This may largely influence on a size of the area of the entire semiconductor memory.
In semiconductor memories with a redundant circuit, high sensitivity sense amplifiers may be provided to all spare cells in a spare row. This largely influence on a size of the entire area of the semiconductor memory.
The followings are a reference documents.    [Patent Document 1] Japanese Laid-open Patent Publication No. 06-36592    [Patent Document 2] Japanese Laid-open Patent Publication No. 01-213990